The invention is generally directed to a semiconductor device including a memory cell array composed of MOS transistors and selection circuitry and in particular to a semiconductor device which provides improved miniaturization and improved speed of operation by reducing the stray capacitance of the bit line.
Reference is made to FIG. 1 wherein a structural block diagram of a semiconductor memory device 100 utilizing MOS transistors is depicted. The address input data is input to memory device 100 at column input terminal 11 and row input terminal 12. The row and column data input to input terminals 11, 12 selects a particular memory cell (MOS transistor) within memory cell array 18. Memory device 100 then outputs the contents of the selected memory cell at data output terminal 13. The row input data entering at row input terminal 12 enters row address input buffer 16 and then row decoder 17 which selects an appropriate row of memory cells and memory cell arrays which are output to bit line select circuit 19. The column address input data which is input to column input terminal 11 moves through column address input buffer 14 to column decoder 15, which selects the appropriate memory cell on the selected row for output to data output circuit 20. Column decoder 15 detects the data written in the memory cell which is output to data output terminal 13.
Row decoder 17 operates by making one row decoder output line, namely the selected word line, equal to a selected level. Likewise, column decoder 15 sets one of the column decoder output lines (bit lines) equal to a selected level, thereby allowing selection of the appropriate word and bit line to which the memory cell specified by the row and column address data is connected. Thus, the selection of the appropriate word line and the appropriate bit line specifies a single memory cell in the array and the contents of that memory cell is detected and output.
The discussions of the semiconductor memory devices, which follows utilizes the example of a Read Only Memory (ROM), although other types of memory devices such as EPROM and EEPROM devices having a floating gate structure among others may be substituted. The ROM structure is used for purposes of explanation as a result of its relative simplicity. In the ROM arrangement, a ROM mask is used to write data to the memory cell which is composed of a MOS transistor. The ROM mask is a photoetching mask which is utilized in the manufacturing process. In memory cells made by utilizing a mask ROM, two methods of manufacture are generally used. The first is the contact window method and the second is the diffusion layer method. In both of these arrangements the memory cell is structured so that the memory cells are connected between a bit line and ground in parallel.
Reference is made to FIG. 2 wherein a memory cell structure in accordance with the diffusion layer method is shown. A word line 59 selects the appropriate row and becomes the gate electrode of the MOS transistor. The oxide film is generally a LOCOS (localized oxidation of silicon) formed of silicon dioxide. Bit lines 60 are formed of a metal material. A difference of an oxide film 62 is used to form the diffusion layer of the MOS transistor. Bit line 60 is coupled to the drain terminal of the MOS transistor (the memory cell) through a contact hole 61. In the semiconductor memory structure of FIG. 2, the diffusion layers forming the source and drain electrodes of the MOS transistor are formed by the self aligned word line 59 and the difference of the oxide film 62. The overlapped portion of word line 59 and oxide film 62 form the channel portion of the MOS transistor. To write data into the structure, the oxide film of the channel portion, which is marked in FIG. 2 with broken line is thickened by masking thereby forming a transistor which will not operate. In this way, depending upon the operability of the MOS transistor, binary information is memorized. That is, a current will either flow through the MOS transistor from the bit line to the ground line or prevent the flow of such current when the gate electrode is energized. The oxide film portion 62 is connected to ground. The same is applicable for the oxide film portion on the opposite side which is not seen in FIG. 2.
Another method of forming a ROM semiconductor memory device is by utilizing an ion implantation method of the type described in Electronic Material, pp. 104-108, January 1986. Reference is made to FIG. 3 wherein a portion of a semiconductor memory device 70 produced in accordance with the ion implantation method is shown. First gate electrodes 63 are formed of a first layer of polycrystalline silicon. Second gate electrodes 64 are formed with second layers of polycrystalline silicon between the first layers of polycrystalline silicon making up first gate electrodes 63. Thus, by also forming transistors between the first gate electrodes, the integrated degree is eliminated. Ion implantation is performed under predetermined electrodes, thereby changing the threshold voltage (portions which are marked with diagonal shading lines in FIG. 3). A bit line 65 is formed of metal. A difference of the oxide film 66 is used to form the diffusion layer and the MOS transistor. Diffusion layer 66 is connected to bit line 65 through a contact hole 67. Group 68 is coupled to a word line and grouping 69 is coupled to a select line for the group of memory cells which are connected in series. In the ROM of FIG. 3, the MOS transistors (which are the memory cells) are connected in series with respect to the ground lines, and memory cell groups (in series) are connected to a bit line in parallel. This type of device is identified as a series-parallel type device.
In the above described generally known ROMs, the impedance between the bit line and the ground line changes in accordance with the existence of the contact hole, the diffusion layer and the particular ion implantation performed. Thus, comparison of the impedance is performed by the bit line and column select circuits, thereby extracting the data from a selected memory cell.
Generally, the minimum size of a design parameter (the design rule) is determined by the accuracy of the photoetching in the manufacturing process. Therefore, in the case of a 2 .mu.m design rule, the width of an electrode is 2 .mu.m, the contact hole is 2 .mu.m and the base size is also 2 .mu.m. However, where portions of the device must overlap other portions in the photoetching process, for example, the overlapped portion of contact hole 61 and the difference of the oxide film 62 and metal bit line 60 (FIG. 2), require expansion of the circuit elements. As a result, it is necessary that contact hole 61 be aligned with respect to oxide film 62 and gate electrode (word line) 59 which has been previously formed. Then the metal must be aligned with respect to the contact hole. As a result, problems with alignment accuracy occur. A spacing margin is thus required around contact hole 61 in oxide film 62 and gate electrode 59 to overcome problems with alignment accuracy and size variation when the oxide film 62 shown in FIG. 2 is formed. As a result, although the design rule is 2 .mu.m, the difference of the oxide film 62 is made considerably larger the 2 .mu.m due to the need to assure alignment with the contact hole. Accordingly the size of the diffusion layer is made about 5 .mu.m, more than twice the size of the design rule to assure reliable manufacturing.
Even where the alignment accuracy of the oxide film and the contact hole can be ignored by forming the diffusion layer by ion implantation after formation of the contact hole, problems with alignment accuracy of the contact hole and the metal still occur which increase the size of the memory cell. Generally, the metal used is aluminum. However, because the aluminum particles are relatively large, the aluminum at the contact portion generally is as large as the size of the oxide film 62.
The series-parallel type ROMs as shown in FIG. 3 have a structure including two layers of gates. That is, they utilize a first gate electode and a second gate electrode which reduces the degree of integration of the memory cells. It is necessary that the spaces in the mask (the portion which will be implanted and are marked with the diagonal lines in FIG. 3) be aligned with the appropriate gate electrodes. As a result, to assure accuracy, the minimum value of the design rule is not utilized and the cell size is increased.
Since the four groups of memory cells connected in series are coupled to one contact in memory device 70 shown in FIG. 3, it is possible to form the oxide film of the memory cell portion, that is the width of the channel region at the minimum value, i.e. at the design rule. However, in order to select one of the two groups of memory cell series by two select lines, ion implantation is performed under one select line, thereby forming a depletion type MOS transistor. Further, on the opposite side, since two groups of the series MOS transistors are connected through the selection circuit in the same manner, the stray capacitance of the diffusion layer of the contact portion and the stray capacitance of the two depletion type MOS transistors are added to the bit line. Thus, in order to connect two groups of the memory cells in series on one side, the diffusion layer whose size is more than three times as large as the minimum dimension of the design rule, is formed on the contact portion. The diffusion layer portion of the contact region extends to the separated portion where the two groups of memory cell series are formed. Thus, even though the width of the channel regions are formed at the minimum value (design rule), the inclusion of the diffusion layer above the MOS transistor portion causes the stay capacitance of the bit line to become extremely large.
As a result, in the series-parallel type of FIG. 3, the MOS transistors are connected in series, thereby increasing the impedance from the bit line 65 to the ground line, making the operation of the series-parallel type device much slower than the parallel type. Moreover, the bit line stray capacitance is substantially increased, causing a further deterioration in the speed of operation. In the parallel type memory structure shown in FIG. 2, half of the contact regions associated with the plurality of memory cells connected to a bit line are added to the stray capacitance of one bit line. This causes a significant deterioration of operating speed due to the large stray capacitance present.
Accordingly, there is a need to speed up the operation of the memory device by reducing the stray capacitance of the bit line and maintaining a highly integrated miniaturized semiconductor memory device at the scale of the design rule.